1. Field of the Invention
The present invention relates to a multiprocessor which can be used as, for example, a parallel computation apparatus and an optical functional device.
2. Related Art of the Invention
With miniaturization and enhancement of functions of electronic devices in recent years, attention has been given to a system-on-chip (SoC) realizing high-density and high-functional packaging using a system LSI in which a semiconductor device of one chip is equipped with a large number of functions (e.g. Japanese Patent Laid-Open No. 2003-188351). In the SoC, a plurality of functions are integrated into one chip with each thereof as a functional block, and functional blocks are interconnected by an internal data bus, and therefore the speed of operations can be enhanced by using the SoC.
Use of the SoC offers various advantages such as an advantage that the speed of operations can be enhanced, while it brings about significant disadvantages in terms of costs, time required for design and development, and the like. Namely, since the circuit size in a semiconductor integrated circuit increases, an increase in the number of man-hours for development, an increase infrequency of debug, and the like raise serious problems. There are cases where it is not inevitable to form all necessary parts as semiconductor integrated circuits, and in addition, if design and development is to be conducted on every occasion in response to upgrades of products, an increase in development cost and a delay of delivery of products tend to occur. Furthermore, there are cases where the SoC cannot be packaged in a product in terms of costs.
In the meantime, aside from the SoC, research and development on a system in packaging (SiP) realizing a high-density and high-functional packaging by forming one package product with one or more semiconductor chip and a plurality of active components and passive components has been vigorously conducted (e.g. Japanese Patent Laid-Open No. 2003-133507). The SiP requires some packaging area compared with the SoC, but allows individual completed devices to be used, and therefore has a significant advantage in terms of costs, time for design and development, and the like.
However, if the SiP is used, the data transmission speed decreases as a whole no matter how fast the data transmission speed in a semiconductor chip because electronic components such as semiconductor chips are interconnected via a wiring board. Namely, in the SoC, functional blocks placed in one chip are interconnected by the internal data bus, and therefore data can be transferred at a high speed, while in the SiP, semiconductor chips within one package are interconnected via the wiring board, and therefore the data transfer speed is limited, thus inevitably decreasing the operation speed.
In this way, both the SoC and SiP have problems, and it is difficult in actuality to solve the problems.
Use of a parallel computer system intended for efficient runs by coupling together a plurality of processors using the above-mentioned SoC and running the processors at a time in parallel, instead of computation processing by a single processor, is under consideration as means meeting a request for enhancement of a calculation capacity (e.g. Japanese Patent Laid-Open No. 6-309285).
However, the parallel computer system described above has a disadvantage that transmission between processors is retarded because a plurality of processors are coupled together. Namely, the data transmission capacity of a data bus in the exterior of a semiconductor element (processor) is low compared with the data transmission capacity of a data bus in the interior of the semiconductor element (processor), and therefore this point is a bottleneck and the computation processing capacity cannot be fully exploited from a viewpoint of an entire system.
Namely, the system having a plurality of processors coupled together, such as the conventional parallel computer system, has a problem such that the computation processing capacity cannot be fully exploited as the entire system.
In consideration of the above problems, the object of the present invention is to provide a multiprocessor having a high data transmission capacity and computation processing capacity as an entire system.